Semiconductor device and method of manufacturing same

ABSTRACT

The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in cross patterns in deep trench regions and improving device yields, and a method of manufacturing the semiconductor device. A semiconductor device includes a LOCOS oxide film which isolates a plurality of diodes in an X direction, and deep trenches which isolate the plurality of diodes in a Y direction. The depth of each of the deep trenches is deeper than a high density layer embedded below a collector layer of each bipolar transistor. A shallow trench may be used as an alternative to the LOCOS oxide film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, andparticularly to a semiconductor device having high adaptability to ahigh speed bipolar process and formed with a highly integratedtransistor array or a diode array, and a method of manufacturing thesemiconductor device.

2. Description of the Related Art

Even of LSIs, a high speed bipolar device has high speed performance andhigh current drive capacity as compared with a CMOS device. Therefore,the high speed bipolar device has the edge over an application-specificdevice. There are known, for example, a laser-driven LSI for opticaltransmission, a power amplifier for a cellular phone, etc. Also the highspeed bipolar device has a high potential in realizing a high-accuracyand a high-sensitive LSI even other than these applications. It can besaid that these are similar not only to analog devices but also todigital devices.

Such a bipolar device has a merit toward actualization of variousleading-edge devices. Of these, some kind of memory-system device orlight-detecting device is capable of bringing out performanceunattainable to CMOS by realizing bipolar devices and a highlyintegrated transistor array or a diode array within the same chip.

A prior art example that realizes such a demand will be explained below.The current typical high-speed bipolar transistor generally adopts anisolation method utilizing LOCOS or a shallow trench and deep trenchesin combination. Each of the deep trenches is buried with a CVD oxidefilm with a view toward minimizing substrate-to-collector capacity.

A schematic sectional structure of a high speed bipolar transistor isshown in FIG. 6(a). A schematic sectional structure of a diode arrayformed over a semiconductor substrate identical to the bipolartransistor is shown in FIG. 6(b). Further, a schematic plan view at thetime that diodes 660 are arranged within the plane in grid form andbrought into integration, is shown in FIG. 6(c).

Here, an N⁺ type buried layer 620 containing As in a high density isformed in a P type silicon substrate 610. An N type epitaxial layer 621that serves as a collector layer is formed on the N⁺ type buried layer620. Deep trenches 630 each buried thereinside with a CVD oxide film areformed in a device isolation region. After etching of the deep trenches630, boron is ion-implanted to form channel stop layers 635 forenhancing a further isolation effect.

A LOCOS oxide film 640 of about 0.7 m is formed around the N typeepitaxial layer 621 to reduce parasitic capacity. Further, according toa self-aligned process, a P type base layer 622 and an N type emitterlayer 623 are formed over the N type epitaxial layer 621 from one mask.Thereafter, a collector electrode 651, an emitter electrode 650 and baseelectrodes 652 that connect the collector layer, emitter layer and baselayer respectively are formed on an insulating film 625. A detailedstructure of a junction portion will not be explained.

The diode shown in FIG. 6(b) can be formed in a process similar to theself-aligned bipolar transistor shown in FIG. 6(a). Thus, a PN junctiondiode is configured in which the emitter electrode 650 of the transistoris provided as a cathode 654 and the base electrode 652 is provided asan anode 653. Here, no LOCOS oxide film is formed inside the diodearray, and the LOCOS oxide film 641 is formed only outside the diodearray. This is because a pattern conversion difference caused by theformation of the LOCOS oxide film is reduced to form a more highlyintegrated array.

A self-aligned contact method for reducing a parasitic capacitor of adevice has been described in a patent document (Japanese UnexaminedPatent Publication No. Hei 6(1994)-318600). In order to relax stress ina device isolation trench region, a method of oxidizing a polysiliconfilm formed within a trench to thereby embed it in the trench has beendescribed in a patent document (Japanese Unexamined Patent PublicationNo. Hei 9(1997)-172061). A method of forming a polysilicon film beforethe formation of a CVD silicon film has been described in a patentdocument (Japanese Unexamined Patent Publication No. 2000-31264). A highwithstand and low on-resistance device in which the depth and open widthof a trench and the width of a current path region have been defined,has been described in a patent document (Japanese Unexamined PatentPublication No. 2002-164540). Further, a method of preventing theoccurrence of a crack without forming a bonding pad over each crosstrench has been described in a patent document (Japanese UnexaminedPatent Publication No. Hei 10(1998)-135454).

However, in the general method of forming the deep trenches in thedevice isolation region and burying the deep trenches with the CVD oxidefilm in the transistors or diode array, a crossed pattern portion C ofthe deep trenches 630 occurs as shown in FIG. 6(c) and the probabilityof occurrence of a crystal defect becomes high at the crossed patternportion of the trenches as distinct from other portions, with the resultthat yields are reduced. The induced cause of the crystal defect resultsfrom going out of stress balance of a trench end with thermal shrinkagein a heat-treating process subsequent to the formation of the CVD oxidefilm.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made in view of such aproblem. An object of the present invention is to provide asemiconductor device which is capable of preventing the occurrence ofcrystal defects in cross patterns in deep trench regions and enhancingdevice yields in transistors and a diode array, and a method ofmanufacturing the semiconductor device.

According to one aspect of the present invention, for achieving theabove object, there is provided a semiconductor device formed with adiode array together with bipolar transistors, wherein diodes areisolated in one direction by a LOCOS oxide film and isolated in theother direction (the direction substantially normal to the onedirection) by trenches. The depth of each of the trenches is a trench(deep trench) deeper than a high density layer embedded below acollector layer of the bipolar transistor.

Trenches (shallow trenches) each deeper than the collector layer andshallower than the high density layer can also be used as an alternativeto the LOCOS oxide film. Since the pitch between the diodes can benarrowed where the shallow trenches are used, high integration isenabled as compared with the case in which the LOCOS oxide film is used.

Since the deep trenches are formed in grid form for the purpose ofdevice-to-device isolation in the conventional diode array, the stressoccurs in each cross pattern portion and the probability of occurrenceof the crystal defects becomes high, thus resulting in a reduction inwafer's yield. In the present invention, however, the LOCOS oxide filmor shallow trenches are used for the device-to-device isolation in onedirection, and the deep trenches are formed only in the direction normalto the one direction. Therefore, the cross patterns of deep trenches arenot formed. Since the LOCOS oxide film and the oxide film embedded ineach shallow trench are thin, it is possible to suppress the occurrenceof stress and reduce the occurrence of crystal defects.

Deep trenches which connect between the deep trenches in T form arefurther added to the above configuration too. Owing to the patternsconnected in T form, the oxide film embedded in each connecting portionbecomes thinner than the cross pattern, whereby stress balance can beheld at less than or equal to an allowable value for the occurrence ofdislocation and the occurrence of crystal defects is reduced.

The deep trenches connecting between the deep trenches in T form areformed every two diodes, and an electrode electrically connected to thehigh density layer is formed between the two diodes, whereby thepotential of the electrode can also be brought or fetched out as acommon potential.

Since the configuration of the electrode and the diode can also beoperated as a transistor wherein the electrode is set as the collectorand the anode and cathode of the diode are respectively set as the baseand emitter, the formation of a transistor array is also enabled.

According to another aspect of the present invention, for achieving theabove object, there is provided a method of manufacturing asemiconductor device, comprising the following steps of sequentiallyforming a first oxide film, a nitride film and a second oxide film overa semiconductor substrate and thereafter forming resist patterns openedin slit form on the second oxide film by photolithography;anisotropically etching the second oxide film, the nitride film and thefirst oxide film with each of the resist patterns as a mask to therebyremove the resist patterns; defining trenches in the semiconductorsubstrate with the second oxide film as a mask; forming a first thermaloxide film over the surface of each of the trenches; forming apolycrystal silicon film over the second oxide film and the firstthermal oxide film of the trench; heat-treating the polycrystal siliconfilm to form a second thermal oxide film; forming a CVD oxide film so asto bury a gap defined in the second thermal oxide film of each trench;exposing the nitride film by an etchback method; and removing thenitride film.

Thus, since the method of forming the thin thermal oxide film insideeach deep trench, forming the thermal oxide film on the formed thermaloxide film by thermal oxidation of thin film polysilicon and burying theremaining gap with the CVD oxide film is used, stress with shrinkage ofthe CVD oxide film almost disappears. The present method is capable ofmore effectively reducing crystal defects by combination with thesemiconductor device based on the above viewpoint.

Further, heat treatment is done after the step of removing the nitridefilm with an etchant, thereby removing moisture from the oxide filmsprovided within the trenches. It is, therefore, possible to reducestress developed in each trench in a subsequent heat-treating processand suppress even the occurrence of crystal defects.

As the CVD oxide film, a low-pressure TEOS (TetraEthylOrthoSilicate)oxide film may preferably be used to bury the gap of the second thermaloxide film.

According to the present invention as described above, cross patterns ofdeep trenches are not formed using a LOCOS oxide film and shallowtrenches. Therefore, thermal shrinkage of an oxide film embedded in eachisolation region is lessened to reduce stress at a trench end andprevent the occurrence of crystal defects, thereby making it possible toenhance device's yields.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming the subject matter which is regarded as theinvention, it is believed that the invention, the objects and featuresof the invention and further objects, features and advantages thereofwill be better understood from the following description taken inconnection with the accompanying drawings in which:

FIG. 1 shows a semiconductor device according to a first embodiment ofthe present invention, wherein FIG. 1(a) is a planar explanatory view,FIG. 1(b) is a cross-sectional view of a portion taken along line A-A inFIG. 1(a), FIG. 1(c) is a cross-sectional view of a portion taken alongline B-B in FIG. 1(a), and FIG. 1(d) is a cross-sectional view of aportion taken along line C-C in FIG. 1(a);

FIG. 2 is a planar explanatory view illustrating a semiconductor deviceaccording to a second embodiment of the present invention;

FIG. 3 is a planar explanatory view showing a semiconductor deviceaccording to a third embodiment of the present invention;

FIG. 4 is a process cross-sectional view showing a method of embeddingdeep trenches, according to a fourth embodiment of the presentinvention, wherein FIG. 4(a) is a view subsequent to the formation ofthe deep trenches, FIG. 4(b) is a view subsequent to the formation ofpolysilicon into the deep trenches, and FIG. 4(c) is a view subsequentto the formation of a thermal oxide film by thermal oxidation of thepolysilicon;

FIG. 5 is a process cross-sectional view showing the method of embeddingthe deep trenches, according to the fourth embodiment, wherein FIG. 5(a)is a view subsequent to embedding of a TEOS film into gaps in the deeptrenches and effecting of full-face etchback thereon, and FIG. 5(b) is aview subsequent to removal of a CVD nitride film; and

FIG. 6 shows a conventional bipolar transistor and diode array, whereinFIG. 6(a) is a schematic cross-sectional view showing the bipolartransistor, FIG. 6(b) is a schematic cross-sectional view showing adiode, and FIG. 6(c) is an explanatory view showing the diode array on aplanar basis.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention will hereinafter bedescribed in detail with reference to the accompanying drawings.Incidentally, elements of structure each having substantially the samefunctional constitution are respectively identified by the samereference numerals in the present specification and the drawings, andthe description of certain common elements of structure will be omitted.

First Embodiment

A first embodiment is shown in FIG. 1. FIG. 1(a) is a view fordescribing the present embodiment on a planar basis. The presentembodiment shows a diode array wherein PN diodes 150 each formed with acathode 154 and an anode 153 are diode-isolated adjacent to one anotherby deep trenches 130 as viewed in one direction (X direction) anddevice-isolated using at least one LOCOS oxide film 140 as viewed in thedirection (Y direction) normal to the one direction. FIG. 1(b) is across-sectional view showing a cross-section of the diode of FIG. 1(a),which is taken along line A-A in FIG. 1(a), FIG. 1(c) is across-sectional view illustrating a cross-section taken along line B-Bin FIG. 1(a), and FIG. 1(d) is a cross-sectional view showing across-section taken along line C-C in FIG. 1(a), respectively.

Here, a sectional structure of the PN diode 150 is similar to FIG. 5(b).A spot equivalent to an emitter electrode of an NPN transistor is formedas a cathode 154, and a spot equivalent to a base electrode thereof isformed as an anode 153. An N⁺ type buried layer 120 corresponding to ahigh density layer is embedded below an N type epitaxial layer 121corresponding to an N type collector layer.

A P type layer (emitter layer in the case of the transistor) is formedover the N type epitaxial layer 121. Thereafter, the N type cathode 154and the P type anode 153 are formed on an insulating film. Since adetailed structure of a junction portion is not important in the presentinvention, its description will be omitted. The thickness of the LOCOSoxide film 140 is set to about 0.7 μm, the width of each deep trench 130is set to about 0.5 μm, and the depth thereof is set to about 3.5 μm,respectively.

Since the LOCOS oxide film is formed shallowly, it separates the N typeepitaxial layer 121 but does not separate the N⁺ type buried layer 120located below the N type epitaxial layer 121. Therefore, theconfiguration of the present embodiment cannot be applied to such atransistor array that current flows through a buried area placed beloweach channel layer. Since current paths are formed in a shallow area onthe surface of a substrate in the case of the diode array, theconfiguration of the present embodiment can be applied to the diodearray.

Thus, since the deep trenches are not formed in lattice or grid form,such cross patterns as shown in FIG. 6(c) are not produced as shown inthe explanatory view of FIG. 1(a). Further, when the high density layer(N⁺ type buried layer 120) placed below the channel layer is formed overthe whole surface of the diode array, the buried layer can provide apotential common to the diodes arranged in respective rows as viewed inthe Y direction. However, the buried areas are perfectly isolated in theadjacent diodes extending in the X direction, which are isolated by thedeep trenches.

Thus, the respective diodes are separated from one another withoutgenerating the cross patterns of the deep trenches. When the crosspatterns exist, stress increases due to a thickened CVD oxide film sothat crystal defects occur. However, if the cross patterns of the deeptrenches are not formed, then a stress balance to an active region ofeach diode is improved so that the probability of occurrence ofdislocation can be greatly suppressed.

As described above, the yields of the highly-integrated diode array canbe greatly improved. Further, since the high density buried layer issupplied with the common potential, the effect of suppressing aparasitic effect is also obtained. Further, although the presentembodiment has explained that it is not possible to carry out theapplication thereof to the transistor array, the present embodiment canbe used as a special-purpose transistor array wherein the high densityburied layer is set as a common collector of a one-way array.

Second Embodiment

A second embodiment is shown in FIG. 2. The present embodiment is onewherein device isolation is carried out by at least one shallow trench142 as an alternative to the device isolation by the LOCOS oxide filmemployed in the first embodiment. The present embodiment is similar tothe first embodiment in other configuration. That is, the presentembodiment shows a diode array in which devices are isolated in onedirection (X direction) by the deep trenches 130 and isolated in thedirection (Y direction) normal to the one direction by the shallowtrench 142.

The depth of the shallow trench is about 0.5 m and an HDP (High DensityPlasma) film of an SiO₂ system is embedded into the shallow trench.Since, however, the shallow trench is planarized using CMP (ChemicalMechanical Polishing) and formed by the known technology, the detaileddescription of a method of forming the shallow trench is omitted.

Since the devices are isolated by using the shallow trench as analternative to the LOCOS oxide film in the present embodiment, the diodepitch in the Y direction can be shortened. Although the LOCOS isolationemployed in the first embodiment needs a 2.5 μm pitch, for example,where a design rule of 0.25 μm is used, a pitch equivalent to almost 2.0μm can be realized where the shallow trench is used.

On the other hand, since the HDP film is a CVD film as distinct from thethermal oxide film employed in the LOCOS method, a slight shrinkageoccurs due to heat treatment in a subsequent process and stressascribable to the shrinkage takes place. Since it leads to theoccurrence of dislocation, the optimization of heat treatment withrespect to the whole process is required.

However, a low pressure TEOS (tetraethoxy silane) film relatively largein water content, which is suitable for embedding a film into each deeptrench, is used in the case of the deep trenches, whereas the HDP filmsuitable for embedding the shallow trench is sufficiently low in watercontent and the level of stress due to the shrinkage is greatly improvedas compared with stress developed in the crossed pattern portion of theconventional deep trenches.

Third Embodiment

A third embodiment is shown in FIG. 3. The present embodiment is onewherein deep trenches for coupling between the deep trenches employed inthe first embodiment are formed. Although the deep trenches are formedin grid form, no cross patterns are formed as in the prior art and thecoupled portions of the deep trenches become T-type patterns. At thistime, the isolation by the shallow trench employed in the secondembodiment may be adopted as an alternative to the isolation by theLOCOS oxide film employed in the first embodiment.

That is, the present embodiment shows a diode array wherein devices areisolated in one direction (X direction) by deep trenches 130 andisolated in the direction (Y direction) normal to the one direction byusing LOCOS oxide films 140 or shallow trenches, and deep trenches 131are formed in the X direction so as to connect between the deep trenches130 every plural diodes, for example, every two diodes in FIG. 3.

As shown in FIG. 3, for example, the deep trenches 131 can be arrangedon both sides of the two diodes adjacent to each other as viewed in theY direction, and collector plugs 160 can be formed as electrodes atintermediate portions of the LOCOS oxide films 140. Thus, the collectorplug 160 can be set to a potential common to the two diodes.

Since transistors can be formed if cathodes 154, anodes 153 and thecollector plugs 160 are configured as emitter electrodes, baseelectrodes and collector electrodes respectively, a transistor array canalso be formed.

Since the deep trenches are formed so as to take the T-type patternsother than the conventional cross patterns upon formation of the deeptrenches in grid form in the present embodiment, a change in thethickness of each locally embedded oxide film can be suppressed, nolarge stress occurs and the occurrence of crystal defects can also besuppressed.

Further, the present structure is different from the prior art in thatthe T-type coupled-portions of the deep trenches are placed inside aLOCOS oxide film region or a shallow trench region. An oxide film layerof the deep trenches and the LOCOS oxide film (or shallow trench) arecapable of effectively relaxing thermal stress developed in emitter andbase junctions that serve as active regions. Further, since the portionat which each deep trench is brought into contact with a substrate,corresponds to a bottom portion of the LOCOS oxide film (or shallowtrench), which is placed in a position deeper than the active junctionregion at which each diode is formed, the occurrence of dislocation canbe suppressed and the influence of dislocation can be lessened evenwhere the dislocation has occurred.

As an application, there is a demand for the use of diodes with two as apair as basic units and a desire to supply a fixed potential even to aburied layer. In such a case, the two diodes adjacent to each other inthe Y direction are used as one pair and the deep trenches are formed onboth sides thereof, thereby enabling their perfect isolation. Further,the whole buried layer can be set to a fixed potential by forming eachof the collector plugs in the LOCOS oxide film (or shallow trench) thatlies midway between the two diodes.

Fourth Embodiment

A method of embedding deep trenches, according to a fourth embodimentwill be explained using process cross-sectional views shown in FIG. 4. ALOCOS oxide film (thermal oxide film) 410 corresponding to a first oxidefilm is laminated on a silicon substrate 400 with a thickness of 0.7 μm,a nitride film 412 is laminated on the LOCOS oxide film 410 with athickness of 0.1 μm by a CVD method, and a CVD oxide film 414corresponding to a second oxide film is laminated on the nitride film412 with a thickness of 0.5 μm, sequentially respectively. Next, resistpatterns for the deep trenches are formed by the known exposuretechnology.

Further, the CVD oxide film 414, the nitride film 412 and the LOCOSoxide film 410 are sequentially removed substantially at rights byanisotropic etching with the resist patterns as masks. Thereafter, theresists are removed and thereafter the silicon substrate 400 is etchedat a depth of about 3.5 μm with the CVD oxide film 414 as a mask to forma deep trench having a width of about 0.5 μm. The so-formed one is shownin FIG. 4(a).

Next, a thermal oxide film 416 corresponding to a first thermal oxidefilm is formed about 500 Å on a silicon surface lying inside the exposeddeep trench by thermal oxidation, and polysilicon 418 is formed over thewhole surface of the silicon substrate 400 with a thickness of about 0.1μm (see FIG. 4(b)). Further, the polysilicon 418 is fully thermallyoxidized. A thermal oxide film 420 corresponding to a second thermaloxide film formed by thermal oxidation reaches a thickness of about 0.2μm (see FIG. 4(c)).

Thus, the interior of the deep trench is buried substantially with thethermal oxide films 416 and 420. Since, however, a small gap less thanor equal to 0.1 μm is defined in the thermal oxide film 420, the gap isburied with a TEOS film 422 corresponding to a CVD oxide film placed ina low pressure state, which is suitable for burying such a portion.Further, heat treatment is done at about 800° C. to dehydrate moisturein the film.

Thereafter, the oxide film is full-face etched back to remove thethermal oxide film 420 and the CVD oxide film 414 deposited over thesurface of the silicon substrate 400. At this time, the nitride film 412is endpoint-detected (i.e., a change of the etching film from the CVDoxide film to the nitride film is detected), whereby etching iscompleted in a state in which the nitride film 412 has been exposed (seeFIG. 5(a)). Further, the nitride film 412 left on the surface is removedby thermal phosphoric acid to thereby realize an isolation structure inwhich the interior of the deep trench is buried with the oxide film (seeFIG. 5(b)).

According to the present embodiment, as distinct from the conventionalmethod for burying the interior of the deep trench with only the TEOSfilm high in embeddability, the deep trench is buried with the thermaloxide film formed on the trench surface and the thermal oxide filmformed by thermal oxidation of the thin film polysilicon formed on thethermal oxide film, and the TEOS film is formed in the gap alone.Therefore, it is possible to reduce stress developed with the shrinkageof the buried film. If heat treatment is further done to dehydrate themoisture in the film, then the stress with the shrinkage of the buriedfilm almost disappears.

Thus, since the stress caused by the insulating film embedded in thedeep trench is suppressed, the probability of occurrence of dislocationcan be greatly reduced. By utilizing the present embodiment and thefirst through third embodiments in combination, a diode array or atransistor array less reduced in crystal defect can be formed inpractice.

Although the preferred embodiments of the present invention have beendescribed above with reference to the accompanying drawings, it isneedless to say that the present invention is not limited to suchembodiments. It will be apparent to those skilled in the art thatvarious changes and modifications can be supposed to be made to theinvention within the scope described in the claims. It should beunderstood that those changes and modifications fall within thetechnical scope of the present invention.

The present invention can be applied to a semiconductor device formedwith a diode array or a transistor array and a method of manufacturingthe semiconductor device. The present invention is applicableparticularly to a diode array or a transistor array which reduces stressdeveloped at an intersecting portion of deep trenches for deviceisolation to thereby lessen the occurrence of crystal defects, and amethod of embedding the deep trenches.

1. A semiconductor device formed with a diode array together withbipolar transistors, comprising: at least one LOCOS oxide film whichisolates one direction of the diode array; and deep trenches whichisolate a direction normal to the one direction of the diode array,wherein the depth of each of the deep trenches is deeper than a highdensity layer embedded below a collector layer of the bipolartransistor.
 2. A semiconductor device according to claim 1, furthercomprising trenches each deeper than the high density layer, each ofwhich connects between the deep trenches in such a manner that aconnecting portion of the deep trenches takes a T type.
 3. Asemiconductor device according to claim 2, wherein the trenchesrespectively connecting between the deep trenches in the T type areformed every adjacent two diodes, and an electrode electricallyconnected to the high density layer is formed between the two diodes. 4.A semiconductor device formed with a diode array together with bipolartransistors, comprising: at least one shallow trench which isolates onedirection of the diode array; and deep trenches which isolate adirection substantially normal to the one direction of the diode array,wherein the depth of each of the deep trenches is deeper than a highdensity layer embedded below a collector layer of the bipolartransistor.
 5. A semiconductor device according to claim 4, furthercomprising trenches each deeper than the high density layer, each ofwhich connects between the deep trenches in such a manner that aconnecting portion of the deep trenches takes a T type.
 6. Asemiconductor device according to claim 5, wherein the trenchesrespectively connecting between the deep trenches in the T type areformed every adjacent two diodes, and an electrode electricallyconnected to the high density layer is formed between the two diodes. 7.A semiconductor device according to claim 6, wherein the electrode andthe diode are constituted as a transistor.
 8. A method of manufacturinga semiconductor device, comprising the following steps of: sequentiallyforming a first oxide film, a nitride film and a second oxide film overa semiconductor substrate and thereafter forming resist patterns openedin slit form on the second oxide film by photolithography;anisotropically etching the second oxide film, the nitride film and thefirst oxide film with each of the resist patterns as a mask to therebyremove the resist patterns; defining trenches in the semiconductorsubstrate with the second oxide film as a mask; forming a first thermaloxide film over the surface of each of the trenches; forming apolycrystal silicon film over the second oxide film and the firstthermal oxide film of the trench; heat-treating the polycrystal siliconfilm to form a second thermal oxide film; forming a CVD oxide film so asto bury a gap defined in the second thermal oxide film of the trench;exposing the nitride film by an etchback method; and removing thenitride film.
 9. A method according to claim 8, further comprising astep for performing heat treatment after the step of removing thenitride film with an etchant, thereby removing moisture from the oxidefilms provided within the trenches.
 10. A method according to claim 8,wherein the CVD oxide film is a TEOS oxide film using a low pressure CVDmethod.